This invention relates generally to floating gate memory devices such as an array of flash electrically erasable programmable read-only memory (EEPROM) cells with redundancy architecture. More particularly, the present invention relates to an improved redundancy architecture for an array of flash EEPROM cells which permit repairing of defective columns of memory cells in the array with spare redundant columns of memory cells on a sector-by-sector basis.
As is generally well known, semiconductor memory devices are manufactured with a memory array of elements which are accessed by a row decoder and a column decoder to address a particular memory element or row of memory elements in the memory array. A sense amplifier is built in the semiconductor chip for sensing the memory state of the selected memory element when addressed by the row decoder and column decoder. In recent years, the density of the memory array on a semiconductor chip has increased to over 1 million memory elements. As the density of the memory array on a semiconductor chip increases, it becomes a significantly more difficult task to produce perfect semiconductor memory chips. In an effort to improve production yields and memory chip reliability, spare or redundant columns of memory cells have been included on the semiconductor chip so as to allow for repairing or replacing defective columns of memory cells in an array.
The semiconductor memory is generally first tested while it is still in a semiconductor wafer joined with other semiconductor memory chips to determine whether it operates properly. If a faulty area is located, extra memory circuits can then be substituted for the defective elements in this faulty area on the primary memory array of memory elements. Typically, circuitry is required for selectively deactivating the defective column of memory cells when repair is desired and for activating a redundant column of memory cells to replace a deactivated column. In order to be able to repair a defect anywhere in the array, the redundant column is required to run the entire length of the array. Previously, column repair was realized in flash EEPROM arrays only on an array-based redundancy where only one defective column in the entire array could be repaired by the redundant column.
Accordingly, there has arisen a need for utilizing the redundant column on a more efficient and effective manner. There has been discovered by the inventors that a sector select transistor could be used to divide and break the redundant column running the entire length of the array into a number of different segments. In this fashion, the different segments of the redundant column residing in the separate sectors are made independent from the other segments in the same redundant column and can thus be used to repair other different defective columns. This type of architecture has the advantage that the amount of space on the semiconductor integrated circuit chip is reduced substantially and thereby decreasing its manufacturing and assembly costs. Further, since each segment is used to repair a smaller area the number of redundant columns needed is less due to the fact that fewer defects will be found in a smaller area. In addition, by reducing the chip area the number of parts, power consumption and heat dissipation can be decreased significantly.
This sector-based redundancy architecture of the present invention is implemented through the use of a plurality of sector select transistors and addressable storage devices. A plurality of sector-based redundancy blocks are provided each having redundant columns of memory cells extending through a plurality of sectors. The sector select transistors serve to divide the redundant columns into a number of different segments. The different segments of the redundant columns residing in the separate sectors are made independent from other segments in the same redundant column and can be thus used to repair a different defective column. The addressable storage devices are used for storing sector-based redundant column addresses containing the defective columns of memory cells in the plurality of sectors in association with one of the different redundant column segments to be used in repairing the defective columns in the corresponding ones of the plurality of sectors.